1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to the cell structure of a dynamic RAM (DRAM), and also to a method of manufacturing the DRAM.
2. Description of the Related Art
The integration density of a MOS-type DRAM, which has memory cells each comprising one MOS transistor and one capacitor, is gradually increasing. The higher the integration density, the smaller the area occupied by the capacitor of each memory cell. The smaller the area of the capacitor, the less charge the capacitor accumulates. Consequently, destruction of the data in the memory cell, generally known as "soft error", is likely to take place.
To solve this problem a method has been proposed. In this method, a larger area is provided for the capacitor of each memory cell so that the capacitor can have greater capacitance to accumulate more charge, without sacrificing the integration density of the DRAM. A capacitor which has a double-stacked storage node is disclosed in T. Kisu et al., "Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell", Extended Abstract of the 20th (1988 International) Conference on Solid-State Devices and Materials, Tokyo, 1988, pp. 581-584. The capacitance of this capacitor is relatively great, but is limited.